1. Field of the Invention
The present invention relates to bit error testing, and more particularly, to an integrated high speed packet bit error test circuit.
2. Related Art
Communicating information via the Internet and other digital communications systems has become common in the United States and elsewhere. As the number of people using these communications systems has increased so has the need for transmitting digital data at ever increasing rates.
As will be understood by persons skilled in the relevant arts, digital communications systems are designed, for example, using look-ahead, pipelining, and parallelism techniques. These known techniques have enabled engineers to build digital communications systems, using available manufacturing technologies, which operate at data rates in excess of 1 Gb/s.
There is a current need for new design techniques and digital logic circuits that can be used to build high-speed digital communication systems. In particular, design techniques and digital logic circuits are needed which can be used to build digital communications circuits that operate at 10 Gb/s and higher.
Testing of the integrity of the communications channel is an important part of any communications system. As transmission speeds increase, the potential for errors generated to channel imperfections, noise, and other factors becomes greater. Currently commercially available systems transmit data at multiple Gigabits per second. For example, the 10 G SERDES (10 Gigabit serializer-deserializer) transmits data on four 2.5 Gigabit channels, for a total of 10 Gigabits/second. Normally, in order to test the error rate of the system, a stand-alone piece of equipment needs to be hooked up to the transmission channel. Test packets are generated by the stand-alone piece of equipment and transmitted through the channel, and are then received back by the stand-alone piece of equipment. The received data is compared to the transmitted data, and the error rate is calculated.
A disadvantage of this approach is the need for a separate piece of equipment that a technician needs to carry around, and the need to “plug it in” into the transmission system in order to test the packet bit error rate. Accordingly, it is desirable to have a packet bit error test capability built into the transmission chip, such as a 10 G SERDES (or higher) chip, that would enable on-the-fly testing of the packet bit error rate of the communications channel.
Furthermore, one of the problems of testing error rate on-the-fly is the high data rate and high clock speeds of a 10 G SERDES communications channel. A 6.4 nanosecond clock, commonly used in the test equipment, translates to 156 megacycles per second. Within the 6.4 nanoseconds available for testing, 80 bits of received data need to be compared to 80 bits of previously transmitted data. Additionally, a 20% margin is required to account for a process variation, therefore, the window for performing the error rate calculation is only 80% of 6.4 nanoseconds. This presents challenges to the designer of a circuit that compares received data with transmitted data, and calculates the bit error rate.